1. Field of the Invention
The present invention relates to a semiconductor device comprising electrically rewritable nonvolatile memory cells.
2. Description of the Related Art
FIG. 26 shows a memory cell structure of a nonvolatile semiconductor memory device using a high dielectric constant insulating film as an inter-electrode insulating film according to the conventional technique (Jpn. Pat. Appln. KOKAI Publication No. 2004-349650). FIG. 26 shows sectional views of nonvolatile memory cells adjacent to each other in a bit line direction (channel length direction).
Floating gate electrodes 93 are provided on a silicon substrate 91 via tunnel insulating films 92, and control gate electrodes 95 are provided on the floating gate electrodes 93 via inter-electrode insulating films 94. Silicon nitride films 96 used as processing masks are provided on the control gate electrodes 95. In addition, source and drain regions 97 are provided on the surface of the silicon substrate 91. And side faces and top faces of gate structure portions each comprising the tunnel insulating films 92, the floating gate electrodes 93, the inter-electrode insulating films 94, the control gate electrodes 95 and the silicon nitride films 96 are covered with a silicon oxide film 98 called an electrode side-wall oxide film and a BPSG (boron phosphorous silicate glass) film 99 as an interlayer insulating film.
Here, the inter-electrode insulating films 94 each include first dielectric regions 941 and second dielectric regions 942 having a lower dielectric constant than that of the first dielectric region 941, and the second dielectric regions 942 are provided on end portions of the first dielectric regions 941 in the channel length direction.
As constituent material for the first dielectric regions 941, alumina or tantalum oxide are disclosed, and as constituent materials for the second dielectric regions 942, silicon oxide, silicon nitride, silicon oxynitride or BPSG are disclosed.
In the memory cell structure, the second dielectric regions 942 having low dielectric constants exist on the top faces of the end portions of the floating gate electrodes 93, thereby, parasitic capacitance between the top faces of the floating gate electrodes 93 owned by adjacent memory cells decreases, effect for avoiding memory malfunction is obtained.
However, due to an existence of the second dielectric regions 942 having low dielectric constants exist, electric capacitance between the top faces of the floating electrodes 93 and bottom faces of the control gate electrodes 95 in the same memory cells decreases, in addition, electric capacitance between the side faces of the floating gate electrodes 93 and the side faces of the control gate electrodes 95 also decreases. Therefore, coupling ratio of the memory cell decreases, and there arises a problem of lowering operation speed of the memory cell.
Here, the coupling ratio is defined as a ratio of voltage applied to the tunnel insulating film to a voltage applied to the control gate, and the ratio is approximately expressed as C2/(C1+C2) if electric capacitance between the substrate and the floating gate is set to C1 and electric capacitance between the floating gate electrode and the control gate electrode is set to C2.